The Laker™ Flat Panel Display Layout Editor from SpringSoft ( http://www.springsoft.com ) has built-in editing functions custom-tailored for flat panel layout, the Laker FPD Layout Editor enables layout engineers to create, route, edit and verify flat panel layout in a single high-performance environment. Four of the top five panel suppliers have adopted the Laker FPD solution for designing various types of flat panel displays.
It reduces cycle times with custom-tailored FPD layout automation and speeds up pixel prototyping by creating parameterized devices that can be reconfigured in seconds. Eliminating the major FPD equal-resistance ro
uting bottleneck, it quickly locates and debugs ERC (electrical rule check) issues.
In a rich and powerful layout environment, Equal Resistance Router makes hundreds of connections quickly and accurately following user-defined patterns and parameters, and resistance Calculator reports routing path resistance of automated and manual routes for immediate feedback of resistance values.
User Defined Device (UDD) speeds up pixel device prototyping, generation and modeling with parameterized device generation that does not require scripting capability. Rule-eriven Editing will automatically check, display, and snap to width, space, notch, overlap, and enclosure rules.
Hierarchical cell placement and reporting capability automatically extracts the alignment mark locations relative to the top-level structure helping you to avoid tedious manual placement of alignment mark cells, and Ptext Generator creates floating polygonal text of specifiable width, from a choice of fonts.
Verification Explorer provides seamless integration with 3rd party physical verification tools such as Calibre® and Hercules™ to browse and debug design rule and LVS violations.