Introduction
Advances in data center technology and Internet usage have pushed enterprise data centers from Gigabit Ethernet links to 10 Gigabit Ethernet (GbE) links and search engines/carriers/ISPs from single 10 GbE links to multiple links. Projected growth indicates the need for higher-speed Internet
connections1. The IEEE 802.3ba task force has been established with the objective of standardizing 100 GbE and 40 GbE over the Internet and within the data center.

If higher-speed Ethernet is to be useful in the near term, implementations must take advantage of existing copper and fiber cables, both in the data center and over the Internet. This poses an interesting problem since no technology currently exists to transport 100 Gbps or 40 Gbps as a single
stream over either media. In order to transport 100 GbE over single-mode fibers, for example, 4 different wavelengths will be required using LAN wavelength-division multiplexing ( LAN WDM).

Similarly, the device interfaces found in routers, switches and servers that drive these higher-speed links cannot currently handle single 100 Gbps or 40 Gbps data streams. They will be forced to resort to parallel electrical “lanes” to handle the flow of data; for example, 10 lanes of 10 Gbps. As technology improves, the bandwidth of fiber wavelengths and electrical lanes will increase at independent rates. Efficient 100 and 40 GbE links will need to handle a number of combinations.

A technique is needed to allow efficient implementation that allows for changing numbers and bandwidths of wavelengths and electrical lanes. Within the 802.3 Ethernet specification, the protocol stack layer that performs this function is called the physical coding sublayer, or PCS. This white paper describes the baseline proposal for the physical coding sublayer (PCS) for the 100-Gbps and 40-Gbps Ethernet interfaces currently under standardization within the IEEE 802.3ba task force.

The Need for PCS Lanes

As discussed earlier, advancing electrical and optical technologies will require the ability to handle differing and changing numbers of electrical interface lanes versus optical lanes. To handle the general case, the PCS baseline proposal calls for data to be distributed on a per-66-bit block
basis to a number of PCS lanes v, where the number of PCS lanes equals the least common multiple of the number of electrical lanes n and optical lanes m.

Using the virtual lane concept, the optical module can be a very simple multiplexer, which merely bit multiplexes the data from electrical lanes down to m media lanes. The receiver’s PCS block can simply demultiplex the data back into the PCS lanes and then realign the skewed data. A virtual lane is a continuous stream of 64/66b blocks. PCS lanes are created through a simple round-robin function which distributes 66-bit blocks, in order, to each virtual lane.

In the case of an interface running with 20 PCS lanes, a single virtual lane would contain every 20th 66-bit block from the aggregate signal, as illustrated in Figure 4 below. In order to allow the receiver to identify and deskew the individual PCS lanes, a unique alignment block is added to each virtual lane on a periodic basis. The alignment block is a special 66-bit control signal block that is unique to each virtual lane and cannot be duplicated in the data. The current proposal under consideration calls for an alignment block once every 16,384 blocks on  each virtual lane.

For details, click PCS_white_paper.pdf