USA - Systems on Silicon Manufacturing Company (SSMC; www.ssmc.com), a Singapore-based joint venture of NXP Semiconductors (www.nxp.com) and Taiwan Semiconductor Manufacturing Company (www.tsmc.com.tw) announced its adoption of Synopsys' (www.synopsys.com) Proteus LRC.
SSMC has deployed Proteus LRC in their production and development flows for post-OPC lithography verification to identify critical manufacturing hotspot locations that are sensitive to process variation and susceptible to increased yield loss.
The hotspots identified by Proteus LRC are fixed prior to committing a design to manufacturing, thereby improving yield ramp, reducing overall development time and resulting in a more reliable process for bringing new products to market.
"This tool enables our design support service team to effectively support our customers during their product development and design validation flow. With Proteus LRC integrated in our chip finishing flow, SSMC is able to consistently and reliably identify manufacturing hotspots early in the prototype tape out phase, when corrective action is most feasible," said Dhruva Kant Shukla, director for product & test engineering at SSMC.
"With deploying Proteus LRC, we are better equipped to deliver our innovative processes in a more robust and reliable way as we progress to smaller technology nodes for specialty wafers required for high performance mixed signal applications."
Proteus LRC delivers industry-leading check algorithms and models to accurately predict the manufacturing process and identify areas in a layout that are not meeting the design intent or are very sensitive to process variation. For easy deployment, Proteus LRC uses the same industry-proven Proteus compact models and Synopsys® Sentaurus Lithography rigorous models used for optical proximity correction (OPC) and process development.
For example, resist top loss and footing are more prevalent at leading-edge nodes and can result in issues during the etch process and ultimately yield loss. Proteus LRC efficiently identifies these areas where resist top loss or footing will occur by using the 3D predictability of these models to provide unique insight into the feature profiles.
Proteus LRC is built on the Proteus engine and integrated into Synopsys' Proteus Pipeline Technology, enabling a single-flow solution from design tapeout to mask fracture. The Pipeline delivers concurrent processing at all stages of the mask synthesis and fracture flow to minimize I/O time for efficient handling of large terabyte datasets encountered at leading-edge technology nodes.
The Proteus engine provides an industry-proven platform that is highly scalable to hundreds, even thousands, of CPUs. This enables control of turnaround time while maintaining the lowest cost of ownership through the use of standard x86 processor cores.
"Proteus LRC consistently delivers industry-leading accuracy that enables companies like SSMC to commit their designs to production with the confidence of knowing they are free of critical manufacturing hotspots," said Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys. "This accuracy and the low cost of ownership have made Proteus LRC the lithography verification solution of choice at leading semiconductor manufacturers worldwide."