Poland - Digital Core Design (www.dcd.pl) introduces the newest hardware implementation of a media access control protocol, defined by the IEEE standard. The DMAC-RMII, in cooperation with an external PHY device, enables network functionality in design. This IP Core supports 10BASE-T and 100BASE-TX/FX IEEE 802.3-2002 compliant RMII PHYs.
The DMAC-RMII Core is able to work with the most popular processors available on the market, either 8., 16. and 32 bit data bus, with little or big endian byte order format. Moreover, it provides static configuration of PHY IC, conforming to the IEEE 802.3-2002 standard.
"We’ve always wanted to design the most “user friendly” solutions, that’s why our DMAC-RMII is also technology independent and thus can be implemented in variety of process technologies," says Jacek Hanke, CEO, Digital Core Design. As the Core has been developed for reuse in ASIC and FPGA projects, it’s been implemented in several commercial products already. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.
When the configurability is just one part of the elusive puzzle, the compatibility issues become cru-cial. That’s why the DMAC-RMII IP Core supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant RMII PHYs. As it’s been stated above, Polish IP Core has a Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers, which ensures maximum compati-bility with a great variety of external CPUs or standard bus controllers.
"As the host interface can be configured to work with 8., 16. or 32-bit data bus lengths with big or little endian order format," explains Hanke, "the DMAC-RMII is compatible with most modern virtual component interfaces."
In addition, AMBA, OCP, OPB and other optional standard interfaces are available, which makes the Core a flexible solution to be utilized in a variety of interface applications, including network devices (eg NICs-Network Interface Cards, routers, switching hubs etc.), embedded microprocessor boards, communication systems and other Systems On Chip (SoC) applications.
DMAC key features :
-Conforms to IEEE 802.3-2002 specification
-8/16/32-bit CPU slave interface with little or big endianess
-Simple interface allows easy connection to CPU
-Narrow address bus with indirect I/O interface to the transmit and receive data dual port memories
-Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant RMII PHYs
-Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers
-Supports full and half duplex operation at 10 or 100 Mbps
-CRC-32 algorithm calculates the FCS nibble at a time, automatic FCS generation and checking, able to capture frame with CRC errors if required
-Lite design, small gate count and fast operation
-Programmable or fixed MAC address
-Promiscuous mode support
-Dynamic PHY configuration by STA management interface
-Receive FIFO able to store many messages at a time
-Allows operation from a wide range of input bus clock frequencies
-Static synchronous design with positive edge clocking and synchronous reset
-No internal tri-states
-Scan test ready