Today’s advanced process technologies create reliability challenges for designers, especially for highly-integrated circuits. Thinner gate oxides and wires coupled with multiple power domains, significantly increase the impact of ESD. Failures are most often only identified in silicon testing, leading to re-designs and re-spins.
Silicon Frontline comes out with the full chip ESD analysis for Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM) events. ESRA (Electrostatic Reliability Analysis) provides a full-chip ESD analysis solution. It delivers extraction, analysis and debugging capability in one integrated environment with the capacity to analyze the full chip. Highlighted violations permit designers to perform corrections at any time in the design process.
ESRA verifies that ESD design guidelines are met, highlights weak areas of designs, reports current density violations and high resistance paths. A graphical environment provides for debugging the violating paths.
ESRA performs analysis on designs in both pre- and post LVS clean, allowing easy identification and correction of issues. A hierarchical debugging methodology provides both telescopic and microscopic views of the design, giving the designer easy access to the level of detail required to effectively make corrections.