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Aldec demonstrates design verification techniques with Hardware-In-The-Loop and QEMU at DvCON China 2017
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2017.04.21  13:10:59
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China - Aldec (www.aldec.com), a pioneer in mixed HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, will present its ASIC pre-silicon Verification Spectrum with hardware-in-the-loop at the DVCon China Conference and Exhibition to be held April 19, 2017, in Shanghai, China.

“The first quarter of this year was a busy and productive one for Aldec R&D. In addition to releasing a new HES board based on the largest Xilinx® Virtex® UltraScale™ FPGA and presenting it at DVCon US, we designed a QEMU Bridge for hardware/software co-simulation of QEMU and Riviera-PRO and unveiled it at Embedded World in Germany to a warm reception,” said Krzysztof Szczur, Aldec Hardware Verification Products Manager.

“The next natural step was to combine the two products and provide a hardware/software co-verification environment with hardware-in-the-loop that connects QEMU and Aldec HES boards. This achievement will be proudly demonstrated at DVCon China in Shanghai.”

Hybrid Co-emulation with QEMU and HES-DVM

A reliable Hardware/Software co-verification technique is indispensable for SoC ASIC verification and validation. QEMU is a generic and open source machine emulator that supports various computer hardware architectures, including ARM® Cortex® families. It can be connected with the Aldec HES-DVM™ emulation platform to provide a complete hybrid co-emulation environment for SoC ASIC designs.

HES-DVM can emulate any part of a design written in synthesizable SystemVerilog or VHDL, most often a custom designed, in-house SoC subsystem implementing unique features of a given SoC. A general purpose processor subsystem (CPU), conversely, is often acquired from a third-party vendor as hard IP or netlist file without RTL code being available.

QEMU is used to emulate standard components such as this, and to run embedded firmware and software tests. It can now be easily connected with the HES-DVM platform, enabling all SoC subsystems to be verified together. This approach guarantees thorough and comprehensive design verification for both hardware and software, without the need for dummy patches or compromising the device driver or firmware code for an otherwise incomplete design.

UVM Simulation Acceleration

Aldec’s 33 years of expertise in HDL simulation and deep understanding of contemporary SoC design/verification demands has paved the way for the development of Aldec’s high-performance HDL simulator, Riviera-PRO™, supporting UVM, SystemVerilog, OSVVM, VHDL-2008 and TLM/SystemC. With Riviera-PRO and hardware-in-the-loop, the simulation can even be two orders of magnitude faster.

The live demo to be presented at DVCon China will demonstrate how to achieve over 130x of simulation acceleration with an example Network on Chip (NoC) design running on a Aldec HES™ FPGA-board driven by a transaction-level UVM Testbench executed in Riviera-PRO.

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