USA - PLX Technology ( http://www.plxtech.com ), the leading global supplier of PCI Express® (PCIe®) switch and bridge silicon, announced two new PLX® ExpressLane™ PCIe Gen 2 switches with low lane counts: the PEX 8604 (four lanes, four ports), PEX 8606 (six lanes, six ports).
The two switches deliver all the unique features available in their higher-lane-count siblings, including the exclusive PLX performancePAK™ and visionPAK™ suites, non-transparency ports, smallest package footprints, and low power requirements. These new low-lane-count PCIe Gen 2 switches are ideal for price-sensitive, mass-production market segments such as set-top boxes, DVRs and multi-function printers.
The new PEX 8604 and PEX 8606 low-lane-count, low-power (0.8W typ.) switches include features such as non-transparency (NT), configurable port flexibility (x1 or x2), true peer-to-peer fan-out, and two virtual channels (VCs) per port that help ensure quality of service (QoS).
All PLX Gen 2 (5GT/s) switches are fully backward-compatible with the PCIe Gen 1 (2.5GT/s) standard, allowing designers to reap the benefits of this higher-performance technology, even in Gen 1-based systems. Design engineers also benefit from the industry`s most advanced software and hardware development kit (SDK/RDK) products developed specifically to support PLX silicon.
"The embedded and consumer markets are squarely in the sites of PCI Express," said Jag Bolaria, senior analyst at the Linley Group. "PLX Technology, with its new low-lane-count switches added to its existing family of switching and bridging devices, is in a good position to capitalize on these new PCI Express applications."
PLX Gen 2 products have set a new high standard with the introduction of its innovative performancePAK capabilities integrated into each switch, including PLX`s Read Pacing™ (intelligent bandwidth allocation) and Dual Cast™ (simultaneously sending data to two ports) features, as well as Dynamic Buffer Allocation (increased throughput by absorbing dynamic increments).
Additionally, the chips include PLX`s unique visionPAK debug diagnostics suite of integrated hardware and software instruments, which consists of a performance monitoring tool, SerDes eye-width measuring, packet generation (for exercising external links at full wire speed) and error injection (to evaluate a system`s ability to detect and recover from such errors).